1. Field of the Invention
The present invention relates to DC-DC converters and, more specifically, to regulation control systems and methods for such converters.
2. Description of Related Art Including Information Disclosed Under 37 CFR 1.97 and 1.98
Driven by faster processors and various silicon chip speeds, the voltage required to power such chips is steadily declining. In the modern telecommunication networks, wireless communication systems, computing and data storage systems, various voltage levels (also called rails) are needed to power various processors, memory chips, application specific IC (ASIC) chips for the best performance. Also, the dc-dc converter power modules required to power the chips may need to be located as close to the chips as possible in order to provide fast load transient response. These non-isolated dc-dc converter modules are referred as Point-of-Loads (POLs).
Over the last two decades, the power electronics industry has managed to significantly improve the power conversion efficiency of the dc-dc converters and POLs thanks to new silicon devices, better ferrite core material, packaging design, and most importantly, the conversion system architecture—the distributed power architecture (see FIG. 1).
A traditional distributed power architecture (DPA) block diagram is shown in FIG. 1. As shown, the AC power (single phase or 3 phases) is converted into a regulated DC voltage, normally at −48V first. This −48V bus is usually isolated from the ac side. A battery bank is connected to the −48V bus to provide the required power back-up in case of ac power failure for critical telecomm, datacomm, and wireless systems. In some cases, where high service availability is not required, then the battery bank can be omitted to save cost and space.
An isolated intermediate bus dc-dc converter (IBC) is inserted between the −48V bus and the point-of-load (POL) dc-dc converters to convert −48V to either regulated 12V or 9.6V or 5V low voltage bus or unregulated 12V, 9.6V or 5V bus since typical POLs operate from either 4.5V to 14V input range or 2.4V to 5.5V input range. The intermediate bus converter can be a fully regulated dc-dc converter or semi-regulated converter or an unregulated converter since the output voltage regulation can be done by various POL converters.
The non-isolated, but fully regulated POL converters then convert the bus voltage to even lower voltage rails to power various required loads such as microprocessors, digital signal processor (DSP), amplifiers, application specific IC chips (ASIC), serial communication devices, etc. Usually. POL converters will achieve the highest efficiency at lower end of input voltage range while the conversion efficiency of the intermediate bus converter (IBC) maximizes at higher output voltage such as 12V. A trade-off needs to be made to select the IBC output voltage in order to achieve the best system level efficiency.
In a modern switch-mode dc-dc converter, the pulse-width modulation technique is used to regulate the converter output voltage. In the case of a full bridge converter (see FIG. 2), when the switch(es) turn on, the input power is delivered (or transferred) to the output side (or secondary side). The switching pulse-width can also be referred to as duty cycle of the switching, and is defined as switch on-time divided by the switching cycle period. The higher the duty cycle, the longer the switch conducting interval, and hence, the more input power is transferred to the output side providing that the switching frequency is constant. Usually when the output voltage is below the desired level due to load change the duty cycle is increased to raise the output voltage so that it stays at the desired level. When the line voltage drops, the output voltage will also dip. By increasing the duty cycle, the output voltage can be maintained.
From the power conversion efficiency point of view, the higher the duty cycle, the better the conversion efficiency. However, for a wide input voltage telecom power system, for example, the −48V bus voltage can vary from −36V to −75V (i.e. 2:1 ratio). Sometimes, it can be 18V to 75V or even wider. The wide range of the input voltage requires the transformer turns ratio to be chosen so that the converter maintains the regulation at minimum input voltage with some voltage margin for the converter internal impedance associated losses. As a result, the converter will have increased primary side current due to low transformer turns ratio and too much voltage available when the input voltage is at highest point. This applies very high voltage stress to the secondary side FETs so that higher voltage rated FETs need to be used (i.e. less efficiency) and requires the converter to operate at very small duty cycle in order to maintain the regulation for a given output voltage. The increased current in the primary winding and power switching FETs also leads to higher conduction and, greater switching losses. Each of these drawbacks causes the dc-dc converter to have lower overall conversion efficiency and requires greater effort to remove the heat that is generated.
In the case of narrow input voltage range applications such as computing and data storage systems, or when the −48V bus is well regulated and not required to have a battery back-up, the intermediate bus converter can be designed differently. Such IBCs can utilize optimal transformer turns ratios and can be operated at nearly fixed duty cycle while allowing the output voltage to vary as the input line voltage and/or output load changes. This is possible because the downstream POL converters can accept wide input voltage range, i.e. 4.5V to 14V, and provide their own regulation for the chip load. This unregulated IBC allows nearly continuous power flow from the input or primary side to the output or secondary side while maintaining the highest possible duty cycle and optimal transformer turns ratio, and hence, the lowest voltage rated secondary switching FETs and the highest conversion efficiency. The concept of fixed duty cycle isolation stages (sometimes referred to as “DC transformers”) combined with switching post regulators (or POLs) has been well known in the industry for decades.
Traditional isolated bus converter designs often include non-regulating isolated full bridge converters followed by several non-isolated post-regulators or non-isolated POLs converters. These full bridge dc-dc converters, such as that shown in FIG. 3, typically operate at approximately 50% fixed duty cycle during the normal and/or steady state operation. The duty cycle is reduced during the non-normal operating states such as during converter start-up or when a current limit is reached. The drawback of this scheme is the wide range variation of the output voltage of the non-regulated isolation stage, especially when the input voltage range is slightly wider such as, for example, 36V to 55V. The output voltage can drop too low, allowing the POLs to draw excessive current from the isolation stage. Consequently, an excessive resistive loss is encountered on the customer printed wiring board (PWB) due to the heavy current in the 12V (nominal) DC distribution bus (or I2R loss). This prevents effective use of such a design in high-power applications.
Another traditional dc-dc converter system design consists of an isolation/semi-regulated forward converter stage followed by several non-isolated post regulators or POLs. In this design the control circuit senses a voltage in the forward converter primary transformer winding circuit to provide a feedback control signal without bridging the primary/secondary isolation barrier. However, because the output voltage is not directly sensed, the output voltage drops as the load current increases due to the impedance of the dc-dc converter.
Although the duty cycle of the forward converter can be slightly adjusted by sensing the primary transformer winding circuit, the output voltage of the isolation stage is still subject to droop. If the input voltage range is relatively wide such as 36V to 75V, the output voltage can vary excessively depending on the main transformer turns ratio. Moreover, the resulting output could be so low at 36V input that it would NOT be suitable for high power application due to heavy current loss in the 12V (nominal) DC distribution bus (i.e., I2R loss).
FIG. 4 presents a graph showing the relationship of the output voltage (Vo) with respect to input voltage (Vin) in an unregulated converter. As shown, the output of such unregulated (402) converters can also be quite high at 75V input such that the output voltage could potentially exceed the downstream POLs input voltage ratings. At a minimum, this high voltage can cause the POLs to operate at quite low conversion efficiency due to very low operation duty cycle and high voltage stress on the switching device. As shown on the graph, unregulated converters do not sense the output voltage, duty cycle is not controlled during normal operation, and the circuit does not control the output voltage toward a predefined value, especially during the output load step change (or load dump). The output voltage swings high during such a transient and the voltage over-shoot level depends on the converter output inductance, the load change slew rate, and the capacitance used in the output of the converter. Similarly, semi-regulated converters do not sense output voltage, but, rather, sense a voltage in the primary winding circuit to infer the output voltage (Vo). Semi-regulated converters also do not have load regulation capability, especially during the output load step change (or load dump). The output voltage swings high during such transients, as depicted. The voltage over-shoot level also depends on the converter output inductance and the capacitance used in the output.
Another known control scheme creates a quasi-regulated converter. FIG. 5 depicts the relationship of the output voltage (Vo) with respect to input voltage (Vin) in a quasi-regulated converter. Quasi regulated converters, as shown, display a region of unregulated operation before and/or after changing modes from regulated or semi-regulated to unregulated. One such design is disclosed in U.S. Pat. No. 7,787,261. The design in this patent is based on a converter that senses only the primary source voltage during the quasi-regulation stage, and fixes the duty cycle of the primary during the unregulated stage. No feedback is provided from the output to the primary circuit, and feedback is not utilized at all during the unregulated stage.
The most common method for using feedback control to tightly regulate converter output is by use of the sensed output voltage signal from the converter output side (or secondary side cross the primary secondary boundary when there is an isolation). FIG. 6 depicts such an arrangement. As depicted, the secondary side output voltage (Voutput) is measured and compared with a precision reference signal (Vref) generated by a costly precision voltage reference chip. The output voltage is then fed to the voltage regulation error-amplifier (U2) to compare with the reference voltage, Vref. The error amplifier, together with various loop compensation circuitry (C2, C3, R13, R15, and C4) are used to regulate the output voltage to achieve regulation accuracy and fast dynamic load response. The output of the error amplifier (U2) is an error signal representing the desired control or regulation intensity (or degree). This error signal is commonly sent to the primary side via an optocoupler (U1). The PWM (pulse-width-modulation) controller at the primary side uses this error signal to regulate the output voltage against the input voltage variation and the output load current variation. Such a feedback control design is exceedingly costly due to the precision components required, and requires substantial amounts of board space due to the large number of discrete components necessary for its implementation.
FIG. 7 depicts another conventional output voltage sensing and feedback scheme that crosses the primary/secondary boundary. This design provides a tightly regulated output (Voutput) as in the design depicted in FIG. 6, but with a shunt regulator (U2) instead of the costly precision reference chip and low offset op-amp of FIG. 6. Regulation may be improved by adding a small capacitor (C2) or a resistor and a capacitor series circuit (R3 and C2) between Vref and the shunt regulator cathode (U2). However, these components, likewise, tend to be relatively costly and bulky in terms of printed wiring board (PWB) space, especially for the POLs load where the tight regulation is not always necessary.
FIG. 8 depicts a graph of the output voltage (Vo) with respect to input voltage (Vin) using a tightly regulated feedback control scheme as depicted in FIGS. 6 and 7. The converter is designed so that for a chosen transformer turns ratio, it can still regulate the output voltage at the pre-defined value with better than +/−3% regulation tolerance over all specified input line, output load, and temperature operating conditions. Turns ratio is defined as Np/Ns, the number of primary turns divided by the number of secondary turns. Again, such designs lead to a small transformer turns ratio, which generates a high primary side current flowing through the transformer winding and the power switching devices, and hence, a relatively poor conversion efficiency. It also applies a high voltage stress to the converter secondary side synchronous rectifier devices, which requires a higher voltage rating device, and hence, the higher the conduction loss and the body diode reverse recovery loss. Furthermore, it requires either an expensive shunt regulator or a precision reference chip and low offset high bandwidth op-amp to achieve this accurate set point control and tight regulation. Since it is difficult to make a fractional turn transformer design, the choice of the transformer turns ratio is limited. For the step-down type of telecomm converter design where a typical source voltage range is from 36V to 75V, the transformer turns ratio is normally an N to 1 design. N can be an integer number such as 2, 3, 4, 5, 6, 7, and 8, etc. depending on the transformer core cross-section area to avoid the core saturation. TDK Innoveta iFA series full brick converter module designed and rolled out in 2001 gives a good example. To utilize the highest possible turns ratio design without losing the output regulation at low end of input source voltage, a 8 to 3 turns ratio was chosen. The converter maintains better than +/−3% tight regulation between 38V to 75V input while allows slightly loose regulation between 36V and 38V. As discussed above, tightly regulated converters are not required for POL loads in today's distributed power architecture.
What is needed is a control scheme that senses the output voltage directly and, in a low-cost way, loosely regulates the output voltage to meet the POL load requirement. Furthermore, this new scheme should utilize a large transformer turns ratio (for instance, N≧4 for a 36V to 75V input and output>8.3V telecomm bus converter system or N≧5 for a 51V to 60V input and output>9.6V bus converter system) to achieve greater conversion efficiency by recognizing that a tightly regulated output voltage is NOT required for POL loads